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| APLUS MAKE YOUR PRODUCTION A-PLUS ASM25512C DATA SHEET APLUS INTEGRATED CIRCUITS INC. Sales E-mail: Mr. Jason sales@aplusinc.com.tw Technology E-mail: Mr. George service@aplusinc.com.tw Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw ASM25512C ASM25512C - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Description The ASM25512C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5.5V Internal Program ROM: 4K x 10-bit 1 sets of 20-bit DPR can access up to 768K x 10 bits data memory space Data Registers: * 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) * Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: * PRA: 4-bit I/O Port A (2Bh) * PRB: 4-bit Output Port B (2Dh) * PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 * Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 The Voice function can be implemented by microprocessor instruction * One 8-bit COUT output for ASM25512C 1 Rev 1.1 2002/10/29 ASM25512C FIGURE 1.1 : Block Diagram of ASM25512C Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[19:12]) =00000000b ADDR[19:0] Stack(12) (2-Level) 0 ROM_ADDR[19:0] 1 DPR3,2,1 DPR[19:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder PCLATCH(8) PCH(8) DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Accumlator(4) Instruction Bus [9:0] SRAM ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh Timer0(9) PRA(4) PRB(4) PRC(4) P1,P2,P3,P4 enter test mode ( Voice synthesizer ) Clock Generator Test select Power on Reset RESET pin PRA0 weak or strong pull-low for PRA, PRB, PRC OSC VDD/GND PRASL(4) One-Channel Reset Chip Reset Chip COUT COUT 2 Rev 1.1 Instruction Bus [9:0] Control Signal 2002/10/29 ASM25512C FIGURE 1.2 : External ROM Map of ASM25512C PC[11:0] 12bit x 2 STACK 20-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing Program and data ROM 00080h-003FFh 00400h 00000h-00FFFh 00000h-BFFFFh 00FFFh(4K) Data ROM BFFFFh(768Kx10-bits) 3 Rev 1.1 2002/10/29 ASM25512C 1.2 Pin-Out ASM25512C Pin-Out VDD3 PRC1 PRC0/RESET PRA3-1 PRA0/RESET I I I I/O I/O STI Std./O.D. STI Std./O.D. STI Std./O.D. STI Std./O.D. Std./O.D. STI Std./O.D. Third Power supply during operation Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-input-floating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-input-floating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Third Circuit Ground Potential OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 GND3 I I O I I O I O I I 1.3 Application circuit 4 Rev 1.1 2002/10/29 ASM25512C 1.4 Bonding Diagram (192K x 10 bit) x 4-Block ROM ASM25512C Y= 4470 + 80 (um) CHIP SIZE: X= 3090 + 80 (um), Y= 4470 + 80 (um) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Substrate must be connected to GND. X= 3090 + 80 (um) ASM25512C Pad Location PAD # PAD Name 1 VDD3 2 PRC1 3 PRC0 4 PRA3 5 PRA2 6 PRA1 7 PRA0/RESET 8 OSC 9 VDD1 10 COUT X -1445.96 -1325.24 -1202.92 -1080.6 -958.28 -835.96 -713.64 -591.32 -416.04 -162.24 Chip Size: X= 3090 + 80 (um) , Y= 4470 + 80 (um) Y PAD # PAD Name X Y -2123.6 11 GND1 38.72 -2118.08 -2123.6 12 GND2 118.72 -2118.08 -2123.6 13 TEST 319.68 -2123.6 -2123.6 14 VDD2 575.32 -2123.6 -2123.6 15 PRB0 714.48 -2123.6 -2123.6 16 PRB1 836.8 -2123.6 -2123.6 17 PRB2 959.12 -2123.6 -2123.6 18 PRB3 1081.44 -2123.6 -2123.6 19 PRC2 1203.76 -2123.6 -2123.6 20 PRC3 1326.08 -2123.6 21 GND3 1449.36 -2123.6 5 Rev 1.1 2002/10/29 ASM25512C 1.5 DC Characteristics for ASM25512C SYMBOL VDD Isb Iop Iih Ioh Iol Cout dF/F dF/F PARAMETER OPERATING VOLTAGE SUPPLY CURRENT STANDBY OPERATING VDD 3 5 3 5 3 5 5 3 5 3 5 3 5 -10 -20 MIN. 2.4 TYP. 3 MAX. 5.5 1 1 UNIT V uA mA uA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT DA CURRENT OUT (FULL SCALE) FREQUENCY STABILITY Fosc VARIATION 2 7 3 9 -5.2 -3 -8 7 20 4 5.2 10 20 mA 4MHz, RM (IO ports) % % Fosc(3v- 2.4v) Fosc (3v) VDD=3V, Rosc=820k, 4MHz FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 1000 3.18 760 4.3 R osc & Freq. 10 Freq. MHz 8 6 4 2 0 0 100 200 300 400 500 600 700 800 900 1000 1100 R osc k ohm 7.89 6.02 4.3 3.18 560 6.02 390 7.89 6 Rev 1.1 2002/10/29 |
Price & Availability of ASM25512C
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